Processing and Characterization of Solderable Interconnection of Power Devices

The most critical challenge in today’s power electronics packaging is the interconnection technology. Inside the state-of-the-art power modules, interconnection of power devices is accomplished with wire bonds, which are prone to noise, parasitic oscillations, fatigue and eventual failure. Bond wires are the major contributors to the package’s resistance; approximately half of the total resistance for the power devices resides in the package components rather than the silicon. The objective of this research is to design direct copper interconnection technique for power electronics modules by eliminating the use of wire bonds. When compared to the wire-bonds, solder interconnects provide larger effective contact areas between power semiconductor devices and overlying power metallization. The larger contact area greatly reduces the current crowding and distributes the mechanical and thermo-mechanical forces over a larger area, thus reducing equivalent mechanical stresses at the device connections. Our thermal and electrical modeling work have suggested that direct solder interconnects will provide the highest packaging density, greatest number of I/Os, shortest possible leads, lowest inductance, highest frequency, best noise control, smallest device footprints, and lowest packaging profile all of which are fundamental towards the implementation of a three-dimensional power module structure.